Methodology Towards Sub-Ppm Testing Of Analog And Mixed-Signal Ics For Cyber-Physical Systems
2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)(2018)
Abstract
Guaranteeing correct and reliable cyber-physical systems requires testing of analog/mixed-signal ICs towards low defect escape rates, below the ppm level. It also requires guaranteeing correct functioning over the product lifetime. However, there are not yet industry-wide automated tools that can generate adequate tests to this end for analog/mixed-signal ICs, like it is currently the case with digital ICs. This paper presents different methods and algorithms that target decreasing defect test escapes in analog/mixed-signal ICs. These methods are based on structural testing for defects, they use fault analysis tools for escape rate analysis and employ DfT structures to increase test coverage, which reduces test escape rate. Furthermore, these structures activate possible latent defect, that may pose threats during the lifetime of integrated circuits.
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Key words
low defect escape rates,structural testing,escape rate analysis,design for testing,fault analysis tools,defect escape rates,subppm testing,cyber-physical systems,mixed-signal integrated circuit,analog integrated circuit,mixed-signal IC
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