A 112-GB/S PAM4 Transmitter in 16NM FinFET

Kee Hian Tan,Ping-Chuan Chiang,Yipeng Wang,Haibing Zhao,Arianne Roldan,Hongyuan Zhao,Nakul Narang,Siok-Wei Lim,Declan Carey,Sai Lalith Chaitanya Ambatipudi,Parag Upadhyaya,Yohan Frans,Ken Chang

2018 IEEE Symposium on VLSI Circuits（2018）

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摘要

This work reports a 112-Gb/s low power voltage-mode transmitter (TX) with four-tap feed forward equalization (FFE), designed and fabricated in 16nm FinFET technology. The design includes a hybrid impedance controller with dual regulator architecture for independent swing, common-mode and equalization control. The 56-Gb/s 4:1 multiplexer (MUX) array together with an automatic phase alignment technique is proposed to minimize output jitter. The TX consumes 345 mW and provides 0.6 to 1-Vpp output swing. The PAM4 TX achieves 130-fs random jitter (RJ) with ratio of level mismatch (RLM) > 0.963.

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关键词

low power voltage-mode transmitter,hybrid impedance controller,dual regulator architecture,independent swing,common-mode,equalization control,4:1 multiplexer array,automatic phase alignment technique,PAM4 transmitter,FinFET technology,PAM4 TX,four-tap feedforward equalization,MUX array,output jitter minimization,size 16.0 nm,power 345.0 mW,bit rate 112 Gbit/s,voltage 0.6 V to 1 V,time 1 fs

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