A Dual-Mode Configurable RF-to-Digital Receiver in 16NM FinFET

A tunable and process-scalable RF-to-digital receiver using a configurable-architecture ADC is implemented in 16nm CMOS. In low-power mode, the 0.7-1.9 GHz receiver is configured as a VCO-based design drawing 9-16 mW and providing -82 dBm sensitivity in a 10 MHz bandwidth. In blocker-tolerant mode, a successive approximation ADC is enabled to obtain an in-band IIP3 of +17 dBm.