An Inverter-Based Analog Front-End for a 56-Gb/s PAM-4 Wireline Transceiver in 16-nm CMOS

This letter describes an inverter-based analog receiver front-end that was evaluated within a complete ADC-based 56-Gb/s four pulse-amplitude modulation wireline transceiver system. The frontend contains hybrid continuous-time linear equalizers with lowand high-frequency peaking as well as inverter-based programmable gain amplifiers that serve as buffers for the 32× time-interleaved SAR ADC. The i...