Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders.

Hazar Yueksel,Matthias Braendli,Andreas Burg,Giovanni Cherubini,Roy D. Cideciyan,Pier Andrea Francese,Simeon Furrer,Marcel A. Kossel,Lukas Kull,Danny Luu,Christian Menolfi,Thomas Morf,Thomas Toifl

IEEE Transactions on Circuits and Systems I: Regular Papers（2018）

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摘要

The implementation of a 25.6-Gb/s four-level pulse-amplitude-modulation (4-PAM) reduced-state sliding-block Viterbi detector (VD) is presented. The power consumption of the VD is 105mW at a supply voltage of 0.7 V, corresponding to an energy efficiency of 4.1 pJ/b. A data rate of 30.4 Gb/s is achieved with an energy efficiency of 5.3 pJ/b at a supply voltage of 0.8 V. The VD, implemented in an exp...

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关键词

Detectors,Decoding,Viterbi algorithm,IEEE 802.3 Standard,EPON,Power demand

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