A 16-Bit Low-Power Double-Sampled Delta Sigma Modulator For Audio Applications

Yongsheng Wang,Hongying Wang,Fengchang Lai,Bei Cao,Yang Liu,Xiaowei Liu

PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON)（2015）

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摘要

This paper presents a 1.8-V 16-bit fourth-order delta sigma modulator for audio applications. Double-sampled structure with DC bias is proposed to double the oversampling ratio in order to improve the resolution without extra demand for the clock frequency, which greatly reduces the power consumption of this system by 50%. Moreover, the gain-enhanced current-mirror amplifier is designed to be the first stage OTA, which decreases the power consumption of the first integrator by 80% compared with a folded-cascode amplifier. With a clock frequency of 3.072MHz and an oversampling ratio of 128, the delta sigma modulator has a signal-to-noise ratio (SNR) of 104.63dB over a bandwidth of 24 kHz. Even when the error ratio of mismatch of sampling paths reaches 1%, the degradation of the SNR is no more than 0.3dB. The power consumption of this modulator is 606 mu W

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关键词

SNR degradation,sampling path mismatch,signal-to-noise ratio,integrator power consumption,OTA,gain-enhanced current-mirror amplifier design,power consumption reduction,oversampling ratio,DC bias,audio applications,fourth-order delta sigma modulator,low-power double-sampled delta sigma modulator,voltage 1.8 V,word length 16 bit

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