3-state BTL closed-loop PWM Class D amplifiers

One of the shortcomings of a number of Class D amplifiers (CDAs) designs is their susceptibility to supply noise, quantified by Power Supply Rejection Ratio (PSRR). Reported investigations thereto to-date remain incomplete/over-simplified, particularly the assumption that the AC ground is noise-less and a simplified fully-differential integrator model. In this paper, the effect of supply noise in the AC ground to PSRR is analytically investigated, and the associated analytical expressions derived. Of specific interest, the analysis is applied to the ubiquitous 3-state Bridge-tied-load (BTL) closed-loop PWM CDA, taking into consideration not only the effect of the non-ideal AC ground, but also the effect of the resistor and capacitor mismatch based on a realistic fully-differential integrator model. Further, the PSRR analysis of 3-state BTL closed-loop CDAs has to date been limited to the single-feedback topology and in this paper, extended to the double-feedback topology. These analyses and derived equations herein are useful as they provide valuable insights to CDA designers into the PSRR mechanisms—for example, the counter-intuitive observation that the CDA with 1st-order integrators provides similar or better PSRR than the CDA with 2nd-order integrators if both CDAs are designed to the same carrier attenuation—including the effect of various circuit parameters, and ensuing trade-offs. The derived analytical expressions are verified by means of HSPICE simulations and on the basis of practical measurements on discretely-realized CDAs.