An Efficient Bayesian Yield Estimation Method for High Dimensional and High Sigma SRAM Circuits

With increasing dimension of variation space and computational intensive circuit simulation, accurate and fast yield estimation of realistic SRAM chip remains a significant and complicated challenge. In this paper, du Experiment results show that the proposed method has an almost constant time complexity as the dimension increases, and gains 6× speedup over the state-of-the- art method in the 485D cases.