A reliable fault detection scheme for the AES hardware implementation

2016 International Symposium on Signal, Image, Video and Communications (ISIVC)(2016)

引用 9|浏览3
暂无评分
摘要
Following the decision to choose Rijndael as the successor of Data Encryption Standard (DES), Advanced Encryption Standard (AES) was increasingly used in numerous applications which require confidentiality and the secure exchange of the data. While security is a property increasingly sought for many applications (credit cards, telecommunications ...), it becomes necessary to consider physical attacks as a source of faults. For example, fault attacks are used to change the behavior of a system and recover meaningful data remain secret. This technique is called Differential Fault Analysis (DFA). To protect the AES algorithm against attacks by fault injection, several fault detection schemes were proposed, which is based on information, hardware or temporal redundancy. In this paper, we implemented the AES algorithm in the encryption process. Also, we proposed a reliable fault detection scheme for the AES algorithm. Our simulations show that the fault coverage of the proposed scheme for single and multiple random errors achieves 99.998%. Moreover, the fault coverage, area overhead, throughput and frequency degradation of our modified AES architecture are also compared to those of the previously reported fault detection schemes.
更多
查看译文
关键词
Hardware Implementation,Fault detection,AES,FPGA
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要