ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures.

Po-Hao Wang,Yung-Chen Chien,Shang-Jen Tsai,Xuan-Yu Lin,Rizal Tanjung,Yi-Sian Lin,Shu-Wei Syu,Tay-Jyi Lin,Jinn-Shyan Wang,Tien-Fu Chen

IEEE Transactions on Very Large Scale Integration (VLSI) Systems（2017）

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摘要

An asymmetric architecture is commonly used in modern embedded systems to reduce energy consumption. The systems tend to execute more applications in the energy-efficient core, which typically employs ultralow voltage (ULV) to save energy. However, caches become a reliability and performance barrier that limits the minimum operating voltage and blocks system performance in the ULV environment. The...

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关键词

Random access memory,Cache memory,Delays,Energy consumption,Computer architecture,Transistors,Discharges (electric)

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