Asynchronous 1R-1W Dual-Port SRAM by Using Single-Port SRAM in 28nm UTBB-FDSOI Technology.
2017 30th IEEE International System-on-Chip Conference (SOCC)（2017）
Key words
clock domain boundaries,dual-port memory architecture,SP-SRAM,Insulator technology,conventional 1R-1W DP-SRAM,single-port SRAM,asynchronous multiport memory,UTBB-FDSOI technology,asynchronous 1R-1W dual-port SRAM,system on chip,write-read ports,dual-port 1R-1W-2RW designs,ultra thin body-box fully depleted silicon on insulator,read-write power consumption,size 28.0 nm,word length 64.0 bit,Si
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