A low-power ESL a-IGZO TFT integrated gate driver circuit

A low-power ESL a-IGZO TFT integrated gate driver, where the gate level of driving-transistor is kept lower than the source/drain level to suppress the serious clock-feed-through effect induced by the large parasitic capacitance of the ESL structured driving TFT. Moreover, a new inverter is designed to minimize internal leakage current Thus, the dependence of power consumption in the gate driver on the overlap-length between gate and source/drain of driving TFT and the bootstrapping capacitor is much lessened Simulation results verify the feasibility of the proposed gate driver with 16 stages and manifest that the power consumption is smaller than half of the conventional one with the same simulation parameters. © (2016) by SID-the Society for Information Display. All rights reserved.