Power proportional adder design for Internet of Things in a 65 nm process

In this paper we present a self-timed, power proportional, 32-bit ripple-carry adder design using a state-of-the art cell library. The cell library implements a new transistor sizing strategy for subthreshold in a commercial 65 nm low power process. Simulation results show improvements in performance and energy per cycle when compared to a fixed-period design. The adder has applications in the internet of things where systems are required to operate over a wide range of conditions and with varying power supplies.