Interleaved Architectures for High-Throughput Synthesizable Synchronization FIFOs

This paper presents a family of FIFOs for clock-domain crossings. These designs are distinguished by an interleaved architecture for the control and data-paths. This approach eliminates most of the throughput bottlenecks in the FIFO design, allowing operation at well over 1GHz in a 65nm process using a standard ASIC design flow. Furthermore, these designs are low-latency: the fall-through time for an empty FIFO is only a few gate delays greater than the synchronizer latency. Our designs are fully synthesizable using widely available design libraries. Furthermore, we identify a glitch vulnerability that is lurking in many published designs, and describe our solutions to these hazards.