Approximate Distributed Arithmetic for Variable-Latency Table Lookup

This paper presents the algorithm and architecture for approximate distribute arithmetic (ADA), which tolerates timing faults in SRAM- or ROM-based lookup tables (LUT) at ultra-low voltages by applying fine-grained bit-slice skipping and compensation. A zero count-based timing fault detector is also proposed, where false-negative detections with seriously decreased SNR are completely avoided. The simulation results show 50.52~57.69dB SNR can be achieved for LUT with 7.82% slow cells (or 3.60~4.47% BER for timing faults, depending on LUT contents), in comparison with 0.21~4.81dB in conventional DA that is not aware of timing faults.