Experiences using a novel Python-based hardware modeling framework for computer architecture test chips

Christopher Torng,Moyang Wang, Bharath Sudheendra, Nagaraj Murali,Suren Jayasuriya,Shreesha Srinath,Taylor Pritchard,Robin Ying,Christopher Batten

2016 IEEE Hot Chips 28 Symposium (HCS)（2016）

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摘要

This poster will describe a taped-out 2×2mm 1.3 M-transistor test chip in IBM 130 nm designed using our new Python-based hardware modeling framework. The goal of our tapeout was to demonstrate the ability of this framework to enable Agile hardware design flows.

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关键词

Python-based hardware modeling framework,computer architecture test chips,agile hardware design flows,1.3 M-transistor test chip,IBM,size 130 nm

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