Dielectric liner reliability in via-middle through silicon vias with 3 Micron diameter

In high aspect ratio through silicon vias (TSV's), the trench step coverage (conformality) of liner, barrier and seed is critical for both the process integration and reliability. If the conformality of a deposition process is improved, the required thickness to be deposited on the field of the wafer can be reduced. Consequently, less material needs to be removed by CMP on the field, which reduces the manufacturing cost. In this paper, the reliability of two liner/barrier/seed options, which were successfully integrated into via-middle TSV's with a diameter of 3µm and an aspect ratio (AR) of 17 is investigated. Both controlled ramp rates (IVctrl) as well as standard Time Dependent Dielectric Breakdown (TDDB) at 100¿C were employed as electrical testing methods to investigate the dielectric and barrier reliability properties of the studied systems. The first studied system consists of a non-conformal CVD O3 TEOS oxide liner, an ALD TiN barrier and a PVD Cu seed. The second studied system employs a conformal ALD oxide liner, a thermal ALD WN barrier and an ELD NiB seed. Both studied systems show excellent reliability properties. Scalable highly conformal liners are more sensitive to local field enhancement at the high fields applied during highly accelerated tests which are far above normal operation conditions. Their performance at lower fields, however, still meets standard reliability specifications. Display Omitted Reliability of two 3×50µm TSV compatible metallization schemes is investigated.TDDB data are impacted by interactions between Si scallops and liner conformality.The scalable one shows more sensitivity to local field enhancement at high field.Their performance at operation fields meets standard reliability specifications.