A Universal Hardware-Driven PVT and Layout-Aware Predictive Failure Analytics for SRAM

The impact of device variability, temperature, and technology CAD-based layout parasitics on low-voltage static random access memory (SRAM) yield is explored using a novel variability-aware statistical methodology. Threshold voltage, Vt, mismatches for planar 22- and 14-nm FinFET SRAM transistors are characterized based on unique array-like structures for capturing process voltage and temperature (PVT) impact on variability. In general, the mismatches are shown to be a consistent and unique function of Vdd, doping, and temperature across the two technologies. Stronger Vt mismatch impact is observed as a function of Vdd and doping in the 22-nm technology, with higher mismatch recorded at lower temperatures. In the 14-nm technology, doping is found to have the strongest impact on Vt mismatch, and the mismatch increases with Vdd despite the reduced drain-induced barrier lowering effects. Similar to the 22-nm technology, the mismatch increases at lower temperatures. Front-end-of-the-line capacitance effects are found to be more significant than back-end-of-the-line effects in 14-nm technologies, as opposed to planar technologies. Accurate parasitic capacitance modeling along with PVT-aware variability process variations for different 22-/14-nm cell arrangements are incorporated into a physics-based statistical analysis methodology for accurate Vmin analysis. The yield analysis results are corroborated with hardware yield using 4-16-Mb inline SRAM macro monitors. The methodology is unique in the industry, gives insight into the technology-circuit interactions, and is able to effectively predict the SRAM yield bounds.