Design and ASIC acceleration of cortical algorithm for text recognition

Cortical algorithms, inspired by the neocortex, promise to outperform conventional algorithms in unsupervised learning tasks, i.e. with unlabeled data. The aim of the work reported in this paper was to design and implement an application specific integrated circuit (ASIC) having a massive speedup of a cortical algorithm, as compared with a CPU baseline. This ASIC is designed to implement a scaled-down version of Sparsey, an algorithm based on structural and functional properties of the brain's cortex. The design was benchmarked on the Short Message Service (SMS) spam collection dataset from the UCI machine learning repository. It was found that the synthesis area and power consumption of a single column (i.e., mac or PE) are 0.122 mm ² and 5.15 mW using 45 nm technology and 0.171 mm ² and 7.94 mW using 65 nm technology. The processing time for a single frame was 3.075 μs (learning) and 0.675 μs (recognition). The performance speedup in learning and recognition modes of ASIC implementation was 203× and 843× times that of software implementation on a CPU based platform.