Sensitivity analysis for SoC performance benchmark against interconnect parasitic resistance and capacitance beyond 10-nm FinFET technology

This paper discusses the performance impact of interconnect parasitic resistance and capacitance for SoC (System on Chip) design beyond 10-nm FinFET technology. As technology scaling advances, the impact of BEOL (Back End of Line) is recognized as one influencer on operating performance. Using typical logic standard cells, sensitivity analysis by DOE (Design of Experiments) shows that the parasitic resistance on wire loads makes a large impact on the cell propagation delay especially with strong cell drivability. Multiple benchmarks show the same tendency that operating performance is degraded by parasitic resistance when strong drivability cells are engaged.