A parallel implementation of deblocking filter based on video array architecture for HEVC

Energy efficiency has become one of the most important topics in computing. High Efficiency Video Coding (HEVC) still adopts the hybrid coding framework. The blocking artifacts still exist and deblocking filter in the HEVC used to reduce the blocking artifacts. Deblocking filter can improve both the subjective and objective video quality, has lowered computational complexity and allows parallel processing. In order to increase the execution efficiency, this paper proposes a parallel implementation of deblocking filter for a 16 ×16 pixel block basis in HEVC standard based on Video Array Architecture, which is programmable and self-reconfigurable driven by energy efficiency, so as to which could achieve high compute performance at a low energy cost. According to the dependence of pixel process, the 16 × 16 pixel block is divided into two types by using 32 thin-core processing elements (TCPE). The experimental results show that the frequency is up to 153.386MHZ synthesized under an XC7Z045 FFG900-2 FPGA chip.