Safety Evaluation Based on Virtual Prototypes: Fault Injection with Multi-Level Processor Models
2016 International Symposium on Integrated Circuits (ISIC)（2016）
Key words
safety evaluation,virtual prototypes,fault injection,multilevel processor models,embedded processors,VP level,ETISS processor simulator,SystemC-TLM VP,RTL level simulation,soft errors,control system,OpenRISC processor
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