A 25 GS/s 6b TI Two-Stage Multi-Bit Search ADC With Soft-Decision Selection Algorithm in 65 nm CMOS.

While high-speed analog-to-digital converter (ADC) front-ends in serial link receivers enable flexible and powerful digital signal processing-based (DSP-based) equalization, the robustness and power consumption of these ADCs can limit overall receiver energy efficiency. This paper presents a 25 GS/s 6b 8-way time-interleaved multi-bit search ADC that employs a soft-decision selection algorithm to ...