20.3 A 100nA-to-2mA successive-approximation digital LDO with PD compensation and sub-LSB duty control achieving a 15.1ns response time at 0.5V

Modern subthreshold SoC designs feature multiple power domains to dynamically track the maximum energy-efficiency point (0.32-0.45V [1]) in response to application demands. While analog low-drop-out (LDO) regulators have shown rapid response times (e.g. T _R = 0.65ns [2]) and excellent steady-state performance, they fail to operate at the low input voltages, V _IN , typically supplied to such SoCs via either a high-efficiency switching DC-DC converter or an external harvesting source (e.g., V _IN = 0.5V). On the other hand, digital LDOs (DLDOs) are becoming popular in low-voltage SoC designs where they can operate reliably from supplies down to 0.5V. However, conventional DLDOs respond slowly to large current steps, especially at low voltages (e.g., T _R = ~44ns, 57.1ns, and 4μs at V _IN =1V [3-5], and 20μs at V _IN =0.5V [1]). Furthermore, they suffer from limited dynamic range over which the load is regulated and stable (e.g. <; 50× [1,4,5]) and occupy a large active area due to barrel-shifter-based control. While slow response can be mitigated with a higher sampling frequency, f _s , this comes at increased power consumption and, importantly, reduced loop stability. To address these issues, this paper presents a 0.5V 0.0023mm ² recursive all-digital LDO (RLDO) in 65nm with hybrid PD-SAR and PWM duty control that achieves 15.1ns and 100ns response and settling times, respectively, while maintaining 5.6mV/mA load regulation and loop stability across a 20,000× dynamic load range, eclipsing state-of-the-art active area, response time, settling time, and dynamic range metrics across prior-art digital LDOs by over an order of magnitude.