Byte-Based Partial-Match instruction and data compression for high-performance and low-power interconnects
2016 14th IEEE International New Circuits and Systems Conference (NEWCAS)(2016)
摘要
With improvement in technology, the number of cores and the numbers of threads per core keep increasing. As a result, instruction and data transferred on interconnects increase significantly. Interconnects are becoming a performance and power bottleneck of multi-core systems. In this paper, we present our compression scheme, Byte-Based Partial-Match (PM) compression for both instruction and data transferred at all memory levels. Our simulation results show that, on average, about 28%~67% compression ratios can be achieved with PM compression. Overall performance of a system can be increased by 1.4%~21.9% with default system bus widths. With compressed bus widths, about 7%~40% of interconnect power can be saved.
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关键词
partial match,compression,power,performance,cache,memory,hit rate,miss rate,Bus-Expander
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