Adding Conditionality to Resilient Bundled-Data Designs
2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)(2016)
Abstract
We describe a practical method of generating production ready timing violation resilient asynchronous circuits with conditional communication from a high level hardware description language. Designs written in SystemVerilogCSP are taped out on a 3.3 million transistor chip. We present two slackless scan-enabled asynchronous controllers based on the Click template that saved an average area of 14% in our application.
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Key words
resilient bundled-data designs,resilient asynchronous circuits,high-level hardware description language,SystemVerilogCSP,transistor chip,slackless scan-enabled asynchronous controllers,click template
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