Hardware Accelerated Search For Resource-Efficient And Secure Permutation Matrices

IEICE ELECTRONICS EXPRESS(2016)

引用 0|浏览5
暂无评分
摘要
Permutation layer is a core component of substitution-permutation network block ciphers. Its design directly affects security and resource usage of the block cipher. It is a challenging problem to find permutation matrices with respect to predefined trade-off targets. In our work, we developed a hardware search engine on Xilinx Virtex-6 FPGA in order to accelerate the search of resource-efficient and secure (maximal branch number) 16 x 16 permutation matrices. Our engine completed the full spectrum search in 129 hours 48 minutes and found non-involutory and involutory permutation matrices with maximal branch number of 5 and minimum Hamming weight (HW) of 74 and 80, respectively. To the best of our knowledge, this is the first time that such a hardware accelerated custom search engine has been built and full spectrum permutation matrix search has been performed.
更多
查看译文
关键词
hardware acceleration, FPGA, symmetric cryptography, block cipher, permutation layer
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要