Predicting Vt mean and variance from parallel Id measurement with model-fitting technique
2016 IEEE 34th VLSI Test Symposium (VTS)(2016)
Abstract
To measure the variation of device V
t
requires long test for conventional WAT test structures. This paper presents a framework that can efficiently and effectively obtain the mean and variance of V
t
for a large number of DUTs. The proposed framework applies the model-based random forest as its core model-fitting technique to learn a model that can predict the mean and variance of V
t
based on only the combined I
d
measured from parallel connected DUTs. The experimental results based on the SPICE simulation of a UMC 28nm technology demonstrate that the proposed model-fitting framework can achieve a more than 99% R-squared for predicting both of V
t
mean and variance. Compared to conventional WAT test structures using binary search, our proposed framework can achieve 42.9X speedup in turn of the required iterations of I
d
measurement per DUT.
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Key words
WAT test structures,wafer acceptance test,model-based random forest,core model-fitting technique,parallel connected DUTs,SPICE simulation,binary search,nMOS transistors
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