A Digital Processor Architecture For Combined Eeg/Emg Falling Risk Prediction

The brain signal anticipates the voluntary movement with patterns that can be detected even 500ms before the occurrence. This paper presents a digital signal processing unit which implements a real-time algorithm for falling risk prediction. The system architecture is designed to operate with digitized data samples from 8 EMG (limbs) and 8 EEG (motor-cortex) channels and, through their combining, provides 1 bit outputs for the early detection of unintentional movements. The digital architecture is validated on an FPGA to determine resources utilization, related timing constraints and performance figures of a dedicated real-time ASIC implementation for wearable applications. The system occupies 85.95% ALMs, 43283 ALUTs, 73.0% registers, 9.9% block memory of an Altera Cyclone V FPGA for a processing latency lower than 1ms. Outputs are available in 56ms, within the time limit of 300ms, enabling decision taking for active control. Comparisons between Matlab (used as golden reference) and measured FPGA outputs outline a very low residual numerical error of about 0.012% (worst case) despite the higher float precision of Matlab simulations and losses due to mandatory dataset conversion for validation.