De Energy Efficient Transceiver In Wireless Network On Chip Architectures

The emergent wireless Network-on-Chip (WiNoC) design paradigm has been proposed as a viable solution for addressing the scalability issues affecting the on-chip communication system in future manycores architectures. Within this scenario, the energy contribution of the buffers (both of the routers and radio-hubs) and the transceivers of the radio-hubs, account for a significant fraction of the total communication energy budget. In this paper, we propose a novel energy management scheme aimed at improving the energy efficiency of a WiNoC architecture based on the selective disabling of the power hungry modules that are predicted being not used during the forthcoming clock cycles. The proposed scheme, applied on different WiNoC topologies with different configurations and under different traffic scenarios, has shown interesting energy saving without any impact on the performance metrics and with a negligible impact on silicon area.