Near-Threshold Circuit Variability In 14nm Finfets For Ultra-Low Power Applications

Sriram Balasubramanian, Ninad Pimparkar,Mangesh Kushare,Vinayak Mahajan, Juhi Bansal,Takashi Shimizu,Vivek Joshi, Kun Qian, Arunima Dasgupta,Karthik Chandrasekaran,Chad Weintraub, Ali Icel

PROCEEDINGS OF THE SEVENTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN ISQED 2016（2016）

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摘要

Ultra low power (ULP) applications use supply voltage (Vdd) scaling as an effective way of reducing power. However, as Vdd is scaled near the threshold voltage (Vt), increased variability limits the minimum Vdd and power that can be realized. This paper outlines a Veff variability framework to capture the total delay variation seen in digital circuits and describes its applicability for near-threshold delay variability analysis. The low-voltage variability framework has been validated against 14nm-FinFET ring oscillator (RO) measurements.

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关键词

CMOS,variability,delay scaling,Ultra-low power,Near-threshold CMOS

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