On-Silicon Validation Of A Benchmark Generation Methodology For Effectively Evaluating Combinational Cell Library Design
2016 17TH IEEE LATIN-AMERICAN TEST SYMPOSIUM (LATS)(2016)
摘要
This work presents the validation in silicon of a test chip for the evaluation of ensembles of combinational CMOS gates (cell library). The design methodology and the architecture of this simple, efficient and easy-to-use test circuit were already proposed theoretically in the past, having been demonstrated its functionality only through partial electrical simulations. The fabrication and measurements over on-silicon prototype provide important information about design improvement possibilities of such a test circuit and its architecture. The results are presented and discussed in this paper.
更多查看译文
关键词
CMOS logic circuit,circuit testing,standard cell library,measurements
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要