Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops.

In this paper, we describe a new approach to reduce dynamic power, leakage, and area of application-specified integrated circuits, without sacrificing performance. The approach is based on a design of threshold logic gates (TLGs) and their seamless integration with conventional standard-cell design flow. We first describe a new robust, standard-cell library of configurable circuits for implementin...