A Top-Down Design Methodology Encompassing Components Variations Due to Wide-Range Operation in Frequency Synthesizer PLLs.

Omar Abdelfattah,George Gal,Gordon W. Roberts,Ishiang Shih,Yi-Chi Shih

IEEE Transactions on Very Large Scale Integration (VLSI) Systems（2016）

引用 6|浏览28

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摘要

This paper presents a complete methodology to model, design, and implement wide tuning-range phase-locked loops (PLLs) using a top-down approach. Mathematical equations that illustrate the contribution of the different sources of noise in the PLL are presented. Behavioral models that encompass the nonidealities of the PLL components are described using Verilog-A language. The PLL components are de...

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关键词

Phase locked loops,Voltage-controlled oscillators,Jitter,Frequency synthesizers,Mathematical model,Predictive models

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