A reconfigurable sense amplifier with 3X offset reduction in 28nm FDSOI CMOS

Symposium on VLSI Circuits-Digest of Papers(2015)

引用 13|浏览24
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摘要
This work proposes an area-efficient approach to fully exploit redundancy in reconfigurable sense amplifiers (SAs). The proposed SA can combine/invert offsets of sub-unit SAs, reducing offset by up to 3.1x at iso-area in 28nm FDSOI.
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关键词
redundancy,reconfigurable sense amplifiers,sub-unit SA,offset reduction,FDSOI CMOS,size 28 nm
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