A quad-channel 112–128 Gb/s coherent transmitter in 40 nm CMOS
VLSIC（2014）
摘要
A quad-channel, 112-128 Gb/s coherent DP-QPSK transmitter in 40 nm CMOS is presented. The 27.9-32.1 Gb/s TX features a half-rate architecture with a 2-tap FIR. The measured output has an amplitude of 1.2Vpp-diff with 1.3 ps deterministic jitter (DJ). The DP-QPSK TX's precoded data alignment is maintained through the quad-lane transmitter by the use of an automatic synchronous feedback loop, removing the need for a master global reset. The PLL outputs the full-rate and half-rate clock with ±0.5 UI skew adjustment relative to the data. The power consumption of the transmitter and PLL is 712 mW.
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关键词
CMOS integrated circuits,FIR filters,circuit feedback,differential phase shift keying,integrated optoelectronics,optical filters,optical modulation,optical transmitters,quadrature phase shift keying,2-tap FIR,CMOS process,DP-QPSK TX precoded data alignment,PLL outputs,UI skew adjustment,automatic synchronous feedback loop,bit rate 112 Gbit/s to 128 Gbit/s,bit rate 27.9 Gbit/s to 32.1 Gbit/s,deterministic jitter,full-rate clock,half-rate architecture,half-rate clock,master global reset,power 712 mW,quad-channel coherent DP-QPSK transmitter,size 40 nm,time 1.3 ps,voltage 0.2 V,
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