A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS

Jafar Savoj,Kenny C.-H. Hsieh,Parag Upadhyaya,Fu-Tai An,Ade Bekele,Stanley Chen,Xuewen Jiang,Kang Wei Lai,Chi Fung Poon, Aman Sewani,Didem Turker, Karthik Venna,Zhaoyin Daniel Wu,Bruce Xu,Elad Alon,Ken Chang

VLSIC（2012）

引用 22|浏览72

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关键词

CMOS logic circuits,decision feedback equalisers,field programmable gate arrays,interference suppression,intersymbol interference,oscillators,radio transceivers,10G-KR characteristics,AFE,bit rate 0.6 Gbit/s to 12.5 Gbit/s,clocking technique,continuous-time linear equalizer,five-tap speculative DFE,long-tail ISI cancellation,loss 33 dB,low-leakage CMOS FPGA,post-cursor ISI,ring oscillators,selective frequency boost,sign-sign LMS algorithm,size 28 nm,three-stage CTLE,three-tap FIR,wide common-mode fully-adaptive multistandard backplane transceiver,wideband LC oscillators,

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