A 60-dB DR PGA with DC-offset calibration for short-distance wireless receiver
VLSI-DAT（2015）
摘要
A low-power, high-linearity programmable gain amplifier (PGA) with DC-offset calibration (DCOC) is presented. The PGA has a large gain range from 5dB to 65dB with 1dB step. Benefited from an improved source-degenerated architecture, the measured gain error is less than 0.15dB. By adopting the closed-loop architecture and resistor array optimization, the PGA achieves an OIP3 of 19.2dBm and an output P1dB of 7.58dBm. Two methods are implemented for DC-offset cancellation: RC high-pass filter (HPF) and digital-assisted DCOC. Implemented in TSMC 0.18um process, the PGA occupies 0.37mm2 die area and consumes 1.82mA (I and Q path) from a 1.7V supply.
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关键词
RC circuits,amplifiers,calibration,high-pass filters,optimisation,programmable circuits,radio receivers,resistors,DC-offset calibration,DC-offset cancellation:,DR PGA,HPF,OIP3,RC high-pass filter,TSMC process,closed-loop architecture,current 1.82 mA,digital-assisted DCOC,gain 1 dB,gain 5 dB to 65 dB,improved source-degenerated architecture,programmable gain amplifier,resistor array optimization,short-distance wireless receiver,size 0.18 mum,voltage 1.7 V,
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