3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS

With the rapid growth of data traffic in data centers, data rates over 50Gb/s/signal (e.g., OIF-CEI-56G-VSR) will eventually be required in wireline chip-to-module or chip-to-chip communications [1-3]. To achieve better power efficiency than that of existing 25Gb/s/signal designs, a high-speed yet energy-efficient front-end is needed in both the transmitter and receiver. A receiver front-end with baud-rate architecture [1] has been successfully operated at 56Gb/s, but additional components such as eye-monitoring comparators, phase detectors, and clock recovery circuitry as well as a power-efficient transmitter are needed to build a complete transceiver.