17.3 A reconfigurable dual-port memory with error detection and correction in 28nm FDSOI

SRAM is a key building block in systems-on-chip and usually limits their voltage scalability, due to the major impact of process/voltage/temperature (PVT) variations at low voltages [1]. Assist techniques to extend SRAM operating voltage range improve the bit cell read/write stability [1-5], but cannot mitigate variations in the internal sensing delay that is needed to develop the targeted bitline (BL) voltage. Hence, large guard bands and performance margins are still needed to ensure correct operation. These margins increase as supply voltage is lowered (Fig. 17.3.1) and must be addressed especially when the SRAM is coupled with margin-less processor designs (e.g., Razor).