10.6 A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS

Injection-locked clock multipliers (ILCMs) achieve superior phase noise compared to conventional PLLs [1, 2]. In its simplest form, an ILCM is an oscillator into which a train of narrow pulses is injected at reference frequency F _REF as shown in Fig. 10.6.1. If the free-running frequency, FFR, of the oscillator is tuned close to NF _REF (N=4, in Fig. 10.6.1), injected pulses phase lock the oscillator and greatly suppress its close-in phase noise. However, any deviation of FFR from NF _REF degrades spurious/jitter performance, making ILCM performance sensitive to PVT variations. A frequency-tracking loop (FTL) was used to continuously tune FFR to be close to NF _REF and achieve excellent jitter performance (<;200fs _rms ) in a power and area efficient manner, independent of PVT variations [1, 2]. However, ILCMs have been fundamentally limited to only integer-N operation and cannot be used for fractional-N frequency synthesis. To understand this limitation, consider the ILCM waveforms shown in Fig. 10.6.1 when FFR is initially tuned to the desired fractional frequency of (N+α)F _REF (N=4 and α=0.25 in the example). Because injection takes place only on the positive edge of reference clock, phase difference between injection pulse and the oscillator output, ΔΦE, grows rapidly at a rate of 0.25T _OSC /T _REF . As a consequence, the oscillator cannot be injection locked and it operates in open-loop mode with poor phase noise/frequency stability. In [3], a coarse fractional-N operation is achieved by rotating the injection across ring oscillator delay stages, but the jitter performance is limited (>4ps _rms ) due to mismatch between delay stages. In this work, we seek to overcome this fundamental limitation of conventional ILCMs and extend their benefits to fractional-N ILCMs.