Kilo-core Wireless Network-on-Chips (NoCs) Architectures

As energy-efficiency and high-performance of Networks-on-Chips (NoCs) communication fabric have become critical, limited bandwidth and fundamental signaling limitations of metallic interconnects have forced academia and industry to consider emerging technologies such as wireless interconnects as an alternate solution. Wireless interconnects offer multiple degrees of freedom for communication without any area overhead for waveguides/wires, and can be built on already available CMOS-RF platforms. In this paper, we propose High-Core WiNoC (HCWiNoC) that can scale to 1000+ cores while mitigating the three critical challenges of WiNoC - limited bandwidth, multi-channel interference and transceiver efficiency - to build an end-to-end solution. First, we describe our row-column HCWiNoC architecture where wireless channels are shared via tokens and wired channels are employed for shorter distances. Second, using HFSS design tool from Ansys, we design monopole and dipole antennas and quantify the multi-channel path loss and dispersion in our WiNoC structure. Third, we describe our transceivers, which consist of local oscillators, on-off keying (OOK) modulators/demodulators, power amplifiers (PA), low-noise amplifiers (LNA) and filters in 65 nm RF-CMOS design from IBM in Cadence Virtuoso. Further, based on our design and published results, we project energy efficiency trends for 32 and 22 nm technology nodes. Our cycle-accurate simulation results on synthetic traffic for 1024 cores indicate that we can double the throughput while consuming 20% lesser power than state-of-the-art WiNoC architecture.