Hardware Accelerator For Minimum Mean Square Error Interference Alignment

A dedicated hardware architecture for the digital baseband processing of minimum mean square error interference alignment is presented. The computationally intensive task of calculating the precoding and decoding matrices has been implemented and the underlying algorithm has been optimized for real-time capability, efficiency and flexibility. The required number of iterations has been optimized and appropriate low-latency algorithms for the computation of basic operations have been identified to meet a real-time constraint of 1 ms processing latency. The architecture has been verified and synthesized for a Xilinx Virtex-6 LX550T FPGA. The maximum number of antennas, users and data streams is configurable at synthesis time. The actual parameters are configurable at runtime. Different degrees of parallelism allow a trade-off between resource requirements, latency and throughput. The target FPGA resources are sufficient for real-time system configurations up to 5 users with 3 antennas.