28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors.

Fady Abouzeid,Sylvain Clerc,Cyril Bottoni,Benjamin Coeffic,Jean-Marc Daveau,Damien Croain,Gilles Gasiot,Dimitri Soussan,Philippe Roche

Proceedings of the European Solid-State Circuits Conference（2015）

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摘要

This paper presents the technology and design optimization performed in 28nm FD-SOI to reach ultra-low energy and/or soft-error tolerance on ARM (R) Cortex (R)-M4 32bits processors. A 8.9pJ per cycle efficiency was measured while performing at 0.5V/45MHz, and a soft-error immunity was measured under alpha and neutron radiation while performing at 1.0V/730MHz. These results were achieved by the design of specific standard cells, macros and clock tree architectures, the technology intrinsic performances, and an adapted CAD flow.

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关键词

FD-SOI technology,SER immune processors,ultralow energy processor,soft error tolerant processor,ARM Cortex M4 processor,clock tree architecture,size 28 nm

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