A High-Performance, Yet Simple To Design, Digital-Friendly Type-I Pll

Analog Type-II phase-locked loops (PLLs) consume large area in loop-filter (LF) and employ noisy and difficult-to-design charge-pump (CP). All-digital PLLs have strict jitter requirements on time-to-digital converters (TDCs). We propose a Type-I PLL that consumes small IT area, requires no bias-generation circuits or CP, and consumes low power. A pulse-width-modulated (PWM) voltage output from the phase-frequency detector (PFD) is fed to a simple RC single-pole LF. Two major limitations of conventional Type-I topologies limited lock-range and large reference spur are overcome by increasing the PFD gain with a combination of a voltage booster and a digital level shifter, and a sample-and-hold (S/H) envelope detector, respectively. Furthermore, a saturated-PFD (SPFD) is proposed to reduce cycle slipping and further improve the lock-range and lock-time. A prototype 2.2-to-2.8 GHz PLL occupies a core area of 0.12 mm(2) in 0.13-mu m CMOS and achieves 490 fs(rms) random jitter, -103.4 dBc/Hz in-band phase noise, -65 dBc reference spur, 2.5 mu s worst-case lock-time while consuming 6.8 mW from a 1.2 V supply.