Comparing Energy, Area, Delay Tradeoffs in Going Vertical with CMOS and Asymmetric HTFETs
2015 IEEE Computer Society Annual Symposium on VLSI（2015）
关键词
Vertical FETs,Standard cell library,cell design,symmetric vertical MOSFETs,tunnel FET,asymmetric vertical TFET,FinFET,Layout,Area,Energy,Delay,trade-off
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