Blade -- A Timing Violation Resilient Asynchronous Template
2015 21st IEEE International Symposium on Asynchronous Circuits and Systems(2015)
摘要
Resilient designs offer the promise to remove increasingly large margins due to process, voltage, and temperature variations and take advantage of average-case data. However, proposed synchronous resilient schemes have either suffered from metastability or require modifying the architecture to add replay-based logic that recovers from timing errors, which leads to high timing error penalties and poses a design challenge in modern processors. This paper presents an asynchronous bundled-data resilient template called Blade that is robust to metastability issues, requires no replay-based logic, and has low timing error penalties. The template is supported by an automated design flow that synthesizes synchronous RTL designs to gate-level asynchronous Blade designs. The benefits of this flow are illustrated on Plasma, a 3-stage Open Core MIPS CPU. Our results demonstrate that a nominal area overhead of the asynchronous template of less than 10% leads to a 19% performance boost over the synchronous design due to average-case data and a 30-40% improvement when synchronous PVT margins are considered.
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关键词
timing violation resilient asynchronous template,temperature variations,average-case data,synchronous resilient schemes,replay-based logic,timing error penalties,asynchronous bundled-data resilient template,metastability issues,gate-level asynchronous Blade designs,Plasma,3-stage OpenCore MIPS CPU,synchronous PVT margins
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