A 14b 35ms/S Sar Adc Achieving 75db Sndr And 99db Sfdr With Loop-Embedded Input Buffer In 40nm Cmos

This paper presents a 14 bit 35 MS/s successive approximation register (SAR) ADC that achieves a nearly constant 74.5 dB peak SNDR up to Nyquist and an SFDR of 90/99 dB for inputs near Nyquist and at low-frequencies, respectively. The ADC employs a loop-embedded input buffer that shields the large sampling capacitor from the input and thereby eases the ADC drive requirements significantly. Since t...