A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation

A 7 bit 2 GS/s flash ADC fabricated in a 65nm CMOS process is presented. The proposed cascaded latch interpolation technique achieves a 4 × interpolation factor with only dynamic comparators. A background latching-time adjustment scheme utilizing a replica latch array ensures an interpolation capability that is robust to process, voltage and temperature variations. The measured peak INL and DNL of...