A 35 dBm Output Power and 38 dB Linear Gain PA With 44.9% Peak PAE at 1.9 GHz in 40 nm CMOS.

IEEE Journal of Solid-State Circuits(2016)

引用 15|浏览57
暂无评分
摘要
This paper presents a 1.9 GHz linear power amplifier (PA) architecture that improves its power efficiency in the power back-off (PBO) region. The combination of power transistor segmentation and digital gain compensation effectively enhances its power efficiency. A fast switching scheme is proposed, such that PA drivers and segments are switched ON and OFF according to signal power; thus, the PA p...
更多
查看译文
关键词
Switches,Baseband,Radio frequency,Power generation,Gain,CMOS integrated circuits,Timing
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要